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A new approach utilizing MOS circuit structures extracted from a circuit net-list for designing VLSI leaf cells is described. A circuit structure is explicitly present in a circuit schematic diagram on which a designer relies for drawing a layout. However, it is absent in the net-list input to an automatic layout system. In this paper, how to extract schematic like information from a net-list and how to apply it for automatic leaf cell design are discussed.

VLSI leaf cell design by understanding circuit structures