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We have designed a 18-bit redundant binary multiplier using pass-transistor logic SPL on a 0.35 /spl mu/m technology. Number of transistors is 12,349, and area is 1322 /spl mu/m/spl times/332 /spl mu/m. Measured power dissipation and maximum delay at T=25/spl deg/C and VDD=3.3 V are 33.7 mW/100 MHz and 7.4 nsec, respectively.

A 16-bit redundant binary multiplier using low-power pass-transistor logic SPL