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This work presents a novel reconfigurable architecture for Low Latency GraphNeural Network (LL-GNN) designs for particle detectors, deliveringunprecedented low latency performance. Incorporating FPGA-based GNNs intoparticle detectors presents a unique challenge since it requiressub-microsecond latency to deploy the networks for online event selection witha data rate of hundreds of terabytes per second in the Level-1 triggers at theCERN Large Hadron Collider experiments. This paper proposes a novelouter-product based matrix multiplication approach, which is enhanced byexploiting the structured adjacency matrix and a column-major data layout.Moreover, a fusion step is introduced to further reduce the end-to-end designlatency by eliminating unnecessary boundaries. Furthermore, a GNN-specificalgorithm-hardware co-design approach is presented which not only finds adesign with a much better latency but also finds a high accuracy design undergiven latency constraints. To facilitate this, a customizable template for thislow latency GNN hardware architecture has been designed and open-sourced, whichenables the generation of low-latency FPGA designs with efficient resourceutilization using a high-level synthesis tool. Evaluation results show that ourFPGA implementation is up to 9.0 times faster and achieves up to 13.1 timeshigher power efficiency than a GPU implementation. Compared to the previousFPGA implementations, this work achieves 6.51 to 16.7 times lower latency.Moreover, the latency of our FPGA design is sufficiently low to enabledeployment of GNNs in a sub-microsecond, real-time collider trigger system,enabling it to benefit from improved accuracy. The proposed LL-GNN designadvances the next generation of trigger systems by enabling sophisticatedalgorithms to process experimental data efficiently.

LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics