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The challenges associated with effectively programming FPGAs have been amajor blocker in popularising reconfigurable architectures for HPC workloads.However new compiler technologies, such as MLIR, are providing new capabilitieswhich potentially deliver the ability to extract domain specific informationand drive automatic structuring of codes for FPGAs.  In this paper we explore domain specific optimisations for stencils, afundamental access pattern in scientific computing, to obtain high performanceon FPGAs via automated code structuring. We propose Stencil-HMLS, amulti-layered approach to automatic optimisation of stencil codes and introducethe HLS dialect, which brings FPGA programming into the MLIR ecosystem. Usingthe PSyclone Fortran DSL, we demonstrate an improvement of 14-100$\times$ withrespect to the next best performant state-of-the-art tool. Furthermore, ourapproach is 14 to 92 times more energy efficient than the next most energyefficient approach.

Stencil-HMLS: A multi-layered approach to the automatic optimisation of stencil codes on FPGA