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There is a long history of side channels in the memory hierarchy of modernCPUs. Especially the cache side channel is widely used in the context oftransient execution attacks and covert channels. Therefore, many secure cachearchitectures have been proposed. Most of these architectures aim to make theconstruction of eviction sets infeasible by randomizing the address-to-cachemapping. In this paper, we investigate the peculiarities of write instructionsin recent CPUs. We identify Write+Write, a new side channel on Intel CPUs thatleaks whether two addresses contend for the same cache set. We show howWrite+Write can be used for rapid construction of eviction sets on currentcache architectures. Moreover, we replicate the Write+Write effect in gem5 anddemonstrate on the example of ScatterCache how it can be exploited toefficiently attack state-of-the-art cache randomization schemes. In addition tothe Write+Write side channel, we show how Write-After-Write effects can beleveraged to efficiently synchronize covert channel communication across CPUcores. This yields the potential for much more stealthy covert channelcommunication than before.

Write Me and I'll Tell You Secrets -- Write-After-Write Effects On Intel CPUs