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To provide data and code confidentiality and reduce the risk of informationleak from memory or memory bus, computing systems are enhanced with encryptionand decryption engine. Despite massive efforts in designing hardwareenhancements for data and code protection, existing solutions incur significantperformance overhead as the encryption/decryption is on the critical path. Inthis paper, we present Sealer, a high-performance and low-overhead in-SRAMmemory encryption engine by exploiting the massive parallelism and bitlinecomputational capability of SRAM subarrays. Sealer encrypts data before sendingit off-chip and decrypts it upon receiving the memory blocks, thus, providingdata confidentiality. Our proposed solution requires only minimal modificationsto the existing SRAM peripheral circuitry. Sealer can achieve up to two ordersof magnitude throughput-per-area improvement while consuming 3x less energycompared to the prior solutions.

Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption