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Pre-silicon side-channel leakage assessment is a useful tool to identifyhardware vulnerabilities at design time, but it requires many high-resolutionpower traces and increases the power simulation cost of the design. Bydownsampling and averaging these high-resolution traces, we show that the powersimulation cost can be considerably reduced without significant loss ofside-channel leakage assessment quality. We introduce a theoretical basis forour claims. Our results demonstrate up to 6.5-fold power-simulation speedimprovement on a gate-level side-channel leakage assessment of a RISC-V SoC.Furthermore, we clarify the conditions under which the averaged samplingtechnique can be successfully used.

Leverage the Average: Averaged Sampling in Pre-Silicon Side-Channel Leakage Assessment