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Performance models that statically predict the steady-state throughput ofbasic blocks on particular microarchitectures, such as IACA, Ithemal, llvm-mca,OSACA, or CQA, can guide optimizing compilers and aid manual softwareoptimization. However, their utility heavily depends on the accuracy of theirpredictions. The average error of existing models compared to measurements onthe actual hardware has been shown to lie between 9% and 36%. But how good isthis? To answer this question, we propose an extremely simple analyticalthroughput model that may serve as a baseline. Surprisingly, this model isalready competitive with the state of the art, indicating that there issignificant potential for improvement.  To explore this potential, we develop a simulation-based throughputpredictor. To this end, we propose a detailed parametric pipeline model thatsupports all Intel Core microarchitecture generations released between 2011 and2021. We evaluate our predictor on an improved version of the BHive benchmarksuite and show that its predictions are usually within 1% of measurementresults, improving upon prior models by roughly an order of magnitude. Theexperimental evaluation also demonstrates that several microarchitecturaldetails considered to be rather insignificant in previous work, are in factessential for accurate prediction.  Our throughput predictor is available as open source athttps://github.com/andreas-abel/uiCA.

uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures