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Accelerating the neural network inference by FPGA has emerged as a popularoption, since the reconfigurability and high performance computing capabilityof FPGA intrinsically satisfies the computation demand of the fast-evolvingneural algorithms. However, the popular neural accelerators on FPGA (e.g.,Xilinx DPU) mainly utilize the DSP resources for constructing their processingunits, while the rich LUT resources are not well exploited. Via thesoftware-hardware co-design approach, in this work, we develop an FPGA-basedheterogeneous computing system for neural network acceleration. From thehardware perspective, the proposed accelerator consists of DSP- and LUT-basedGEneral Matrix-Multiplication (GEMM) computing cores, which forms the entirecomputing system in a heterogeneous fashion. The DSP- and LUT-based GEMM coresare computed w.r.t a unified Instruction Set Architecture (ISA) and unifiedbuffers. Along the data flow of the neural network inference path, thecomputation of the convolution/fully-connected layer is split into twoportions, handled by the DSP- and LUT-based GEMM cores asynchronously. From thesoftware perspective, we mathematically and systematically model the latencyand resource utilization of the proposed heterogeneous accelerator, regardingvarying system design configurations. Through leveraging the reinforcementlearning technique, we construct a framework to achieve end-to-end selectionand optimization of the design specification of target heterogeneousaccelerator, including workload split strategy, mixed-precision quantizationscheme, and resource allocation of DSP- and LUT-core. In virtue of the proposeddesign framework and heterogeneous computing system, our design outperforms thestate-of-the-art Mix&Match design with latency reduced by 1.12-1.32x withhigher inference accuracy. The N3H-core is open-sourced at:https://github.com/elliothe/N3H_Core.

N3H-Core: Neuron-designed Neural Network Accelerator via FPGA-based Heterogeneous Computing Cores