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Specialized hardware accelerators have been designed and employed to maximizethe performance efficiency of Spiking Neural Networks (SNNs). However, suchaccelerators are vulnerable to transient faults (i.e., soft errors), whichoccur due to high-energy particle strikes, and manifest as bit flips at thehardware layer. These errors can change the weight values and neuron operationsin the compute engine of SNN accelerators, thereby leading to incorrect outputsand accuracy degradation. However, the impact of soft errors in the computeengine and the respective mitigation techniques have not been thoroughlystudied yet for SNNs. A potential solution is employing redundant executions(re-execution) for ensuring correct outputs, but it leads to huge latency andenergy overheads. Toward this, we propose SoftSNN, a novel methodology tomitigate soft errors in the weight registers (synapses) and neurons of SNNaccelerators without re-execution, thereby maintaining the accuracy with lowlatency and energy overheads. Our SoftSNN methodology employs the following keysteps: (1) analyzing the SNN characteristics under soft errors to identifyfaulty weights and neuron operations, which are required for recognizing faultySNN behavior; (2) a Bound-and-Protect technique that leverages this analysis toimprove the SNN fault tolerance by bounding the weight values and protectingthe neurons from faulty operations; and (3) devising lightweight hardwareenhancements for the neural hardware accelerator to efficiently support theproposed technique. The experimental results show that, for a 900-neuronnetwork with even a high fault rate, our SoftSNN maintains the accuracydegradation below 3%, while reducing latency and energy by up to 3x and 2.3xrespectively, as compared to the re-execution technique.

SoftSNN: Low-Cost Fault Tolerance for Spiking Neural Network Accelerators under Soft Errors