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In this paper, we present an energy-efficient SNN architecture, which canseamlessly run deep spiking neural networks (SNNs) with improved accuracy.First, we propose a conversion aware training (CAT) to reduce ANN-to-SNNconversion loss without hardware implementation overhead. In the proposed CAT,the activation function developed for simulating SNN during ANN training, isefficiently exploited to reduce the data representation error after conversion.Based on the CAT technique, we also present a time-to-first-spike coding thatallows lightweight logarithmic computation by utilizing spike time information.The SNN processor design that supports the proposed techniques has beenimplemented using 28nm CMOS process. The processor achieves the top-1accuracies of 91.7%, 67.9% and 57.4% with inference energy of 486.7uJ, 503.6uJ,and 1426uJ to process CIFAR-10, CIFAR-100, and Tiny-ImageNet, respectively,when running VGG-16 with 5bit logarithmic weights.

A Time-to-first-spike Coding and Conversion Aware Training for Energy-Efficient Deep Spiking Neural Network Processor Design