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This paper proposes a methodology for designing sampled-data Mixed-Signal circuits by using VHDL-based behavioural descriptions. The goal is using a VHDL description of both the analog and the digital part, to simulate and verify the entire mixed-signal system, as well as to facilitate the synthesis and fault simulation of the digital part. As an example of the proposed methodology, a digitally corrected/calibrated pipeline A/D converter (ADC) has been designed. Among other aspects of general interest, we will show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. Results from simulations carried out using QuickHDL in MentorGraphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype. In this paper we will show how VHDL can be efficiently used to simulate and verify the functionality of digitally corrected/calibrated pipeline ADCs. Having achieved this, the digital part of the VHDL may be synthesized with a high confidence in that the entire system will operate as intended. In addition, analysing the fault coverage of this part is facilitated, and the basis for a solution to test program generation is provided. Our motivation originates from the need of synthesizing the digital part of the pipeline ADC with enhanced testability proposed in [3]. The complexity of the digital circuit derives, in this case, from the incorporation of correction, calibration, and control of different testing modes. Verifying all the operation modes of the system in an early phase of design and having the possibility to quickly perform modifications (or to prove alternative calibration algorithms) leads us to develop the VHDL-based behavioural model of the whole system. This model must be simple but at the same time sufficiently precise and detailed to be able to predict static and dynamic performance. There exists other additional incentives making particularly interesting the VHDL description of the analog part in this converter design. One of them derives from the requirement of an exhaustive set of realistic patterns coming from the analog part and needed to verify the digital part. Although these patterns can be separately obtained with other software tool, in some modes of operation, as for instance under digital calibration, the generation of input patterns for the digital subsystem is intimately dependent of the control that the digital part has on the analog part. These situations where a feedback loop exists between the digital and analog processes are difficult to verify using separate simulation tools.

A VHDL-based methodology for the design and verification of pipeline A/D converters