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Modern computing systems are embracing hybrid memory comprising of DRAM andnon-volatile memory (NVM) to combine the best properties of both memorytechnologies, achieving low latency, high reliability, and high density. Aprominent characteristic of DRAM-NVM hybrid memory is that it has NVM accesslatency much higher than DRAM access latency. We call this inter-memoryasymmetry. We observe that parasitic components on a long bitline are a majorsource of high latency in both DRAM and NVM, and a significant factorcontributing to high-voltage operations in NVM, which impact their reliability.We propose an architectural change, where each long bitline in DRAM and NVM issplit into two segments by an isolation transistor. One segment can be accessedwith lower latency and operating voltage than the other. By introducing tiers,we enable non-uniform accesses within each memory type (which we callintra-memory asymmetry), leading to performance and reliability trade-offs inDRAM-NVM hybrid memory. We extend existing NVM-DRAM OS in three ways. First, weexploit both inter- and intra-memory asymmetries to allocate and migrate memorypages between the tiers in DRAM and NVM. Second, we improve the OS's pageallocation decisions by predicting the access intensity of a newly-referencedmemory page in a program and placing it to a matching tier during its initialallocation. This minimizes page migrations during program execution, loweringthe performance overhead. Third, we propose a solution to migrate pages betweenthe tiers of the same memory without transferring data over the memory channel,minimizing channel occupancy and improving performance. Our overall approach,which we call MNEME, to enable and exploit asymmetries in DRAM-NVM hybridtiered memory improves both performance and reliability for both single-coreand multi-programmed workloads.

Exploiting Inter- and Intra-Memory Asymmetries for Data Mapping in Hybrid Tiered-Memories