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High Level Synthesis (HLS) tools, like the Intel FPGA SDK for OpenCL, improvedesign productivity and enable efficient design space exploration guided bysimple program directives (pragmas), but may sometimes miss importantoptimizations necessary for high performance. In this paper, we present a studyof the tradeoffs in HLS optimizations, and the potential of a modern HLS toolin automatically optimizing an application. We perform the study on a 5-stagecamera ISP pipeline using the Intel FPGA SDK for OpenCL and an Arria 10 FPGADev Kit. We show that automatic optimizations in the HLS tool are valuable,achieving a up to 2.7X speedup over equivalent CPU execution. With further handtuning, however, we can achieve up to 36.5X speedup over CPU. We draw severalspecific lessons about the effectiveness of automatic optimizations guided bysimple directives, and the nature of manual rewriting required for highperformance.

Studying the Potential of Automatic Optimizations in the Intel FPGA SDK for OpenCL