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We propose two tiers of modifications to FPGA logic cell architecture todeliver a variety of performance and utilization benefits with only minor areaoverheads. In the irst tier, we augment existing commercial logic celldatapaths with a 6-input XOR gate in order to improve the expressiveness ofeach element, while maintaining backward compatibility. This new architectureis vendor-agnostic, and we refer to it as LUXOR. We also consider a secondarytier of vendor-speciic modifications to both Xilinx and Intel FPGAs, which werefer to as X-LUXOR+ and I-LUXOR+ respectively. We demonstrate that compressortree synthesis using generalized parallel counters (GPCs) is further improvedwith the proposed modifications. Using both the Intel adaptive logic module andthe Xilinx slice at the 65nm technology node for a comparative study, it isshown that the silicon area overhead is less than 0.5% for LUXOR and 5-6% forLUXOR+, while the delay increments are 1-6% and 3-9% respectively. Wedemonstrate that LUXOR can deliver an average reduction of 13-19% in logicutilization on micro-benchmarks from a variety of domains.BNN benchmarksbenefit the most with an average reduction of 37-47% in logic utilization,which is due to the highly-efficient mapping of the XnorPopcount operation onour proposed LUXOR+ logic cells.

LUXOR: An FPGA Logic Cell Architecture for Efficient Compressor Tree Implementations