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This paper aims at integrating three powerful techniques namely DeepLearning, Approximate Computing, and Low Power Design into a strategy tooptimize logic at the synthesis level. We utilize advances in deep learning toguide an approximate logic synthesis engine to minimize the dynamic powerconsumption of a given digital CMOS circuit, subject to a predetermined errorrate at the primary outputs. Our framework, Deep-PowerX, focuses on replacingor removing gates on a technology-mapped network and uses a Deep Neural Network(DNN) to predict error rates at primary outputs of the circuit when a specificpart of the netlist is approximated. The primary goal of Deep-PowerX is toreduce the dynamic power whereas area reduction serves as a secondaryobjective. Using the said DNN, Deep-PowerX is able to reduce the exponentialtime complexity of standard approximate logic synthesis to linear time.Experiments are done on numerous open source benchmark circuits. Results showsignificant reduction in power and area by up to 1.47 times and 1.43 timescompared to exact solutions and by up to 22% and 27% compared tostate-of-the-art approximate logic synthesis tools while having orders ofmagnitudes lower run-time.

Deep-PowerX: A Deep Learning-Based Framework for Low-Power Approximate Logic Synthesis