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Important workloads, such as machine learning and graph analyticsapplications, heavily involve sparse linear algebra operations. Theseoperations use sparse matrix compression as an effective means to avoid storingzeros and performing unnecessary computation on zero elements. However,compression techniques like Compressed Sparse Row (CSR) that are widely usedtoday introduce significant instruction overhead and expensive pointer-chasingoperations to discover the positions of the non-zero elements. In this paper,we identify the discovery of the positions (i.e., indexing) of non-zeroelements as a key bottleneck in sparse matrix-based workloads, which greatlyreduces the benefits of compression. We propose SMASH, a hardware-softwarecooperative mechanism that enables highly-efficient indexing and storage ofsparse matrices. The key idea of SMASH is to explicitly enable the hardware torecognize and exploit sparsity in data. To this end, we devise a novel softwareencoding based on a hierarchy of bitmaps. This encoding can be used toefficiently compress any sparse matrix, regardless of the extent and structureof sparsity. At the same time, the bitmap encoding can be directly interpretedby the hardware. We design a lightweight hardware unit, the Bitmap ManagementUnit (BMU), that buffers and scans the bitmap hierarchy to performhighly-efficient indexing of sparse matrices. SMASH exposes an expressive andrich ISA to communicate with the BMU, which enables its use in accelerating anysparse matrix computation. We demonstrate the benefits of SMASH on four usecases that include sparse matrix kernels and graph analytics applications.

SMASH: Co-designing Software Compression and Hardware-Accelerated Indexing for Efficient Sparse Matrix Operations