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This paper proposes a novel cache-memory design for soft-error silence, and verifies the design through a simulation that uses realistic system and software model. The SSI design is a combination of an n-bit error detector and a fast circuit that allows real-time-forced invalidation of corrupted data sets. The current design supports the write through caching policy and will be extended for the write back policy. To verify the effectiveness of the proposed design approach, mixed-mode simulations are conducted that insert soft-errors(bit-flips) into the cache-memory model. The simulation commences while running different class of programs (ALU-intensive and branch-intensive programs) designed to stress several key functions of the target system. System-level failure modes triggered by the soft errors are observed and all inserted errors are recovered by SSI scheme. The performance and layout-area overheads are also quantified. The worst-case performance/time overhead of the SSI scheme is approximately 9% while the lay-out-area overhead is less than 0.5%

Selective-set-invalidation (SSI) for soft-error-resilient cache architecture