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The International Technology Roadmap for Semiconductors (ITRS) projects that by 2011 over one billion transistors will be integrated into a single monolithic die. The wiring system of this billion-transistor die will deliver power to each transistor, provide a low-skew synchronizing clock to latches and dynamic circuits, and distribute data and control signals throughout the chip. The resulting design and modeling complexity of this GSI multilevel interconnect network is enormous such that over 10 coupling inductances and capacitances throughout a nine-to-ten level metal stack must be managed. This discussion session will focus on system-level limits that on-chip signal interconnects place upon a GSI product design in the 21 century.

Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session)