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In this work, we introduce a platform for register-transfer level (RTL)architecture design space exploration. The platform is an open-source,parameterized, synthesizable set of RTL modules for designing RISC-V basedsingle and multi-core architecture systems. The platform is designed with ahigh degree of modularity. It provides highly-parameterized, composable RTLmodules for fast and accurate exploration of different RISC-V based corecomplexities, multi-level caching and memory organizations, system topologies,router architectures, and routing schemes. The platform can be used for bothRTL simulation and FPGA based emulation. The hardware modules are implementedin synthesizable Verilog using no vendor-specific blocks. The platform includesa RISC-V compiler toolchain to assist in developing software for the cores, aweb-based system configuration graphical user interface (GUI) and a web-basedRISC-V assembly simulator. The platform supports a myriad of RISC-Varchitectures, ranging from a simple single cycle processor to a multi-core SoCwith a complex memory hierarchy and a network-on-chip. The modules are designedto support incremental additions and modifications. The interfaces betweencomponents are particularly designed to allow parts of the processor such aswhole cache modules, cores or individual pipeline stages, to be modified orreplaced without impacting the rest of the system. The platform allowsresearchers to quickly instantiate complete working RISC-V multi-core systemswith synthesizable RTL and make targeted modifications to fit their needs. Thecomplete platform (including Verilog source code) can be downloaded athttps://ascslab.org/research/briscv/explorer/explorer.html.

BRISC-V: An Open-Source Architecture Design Space Exploration Toolbox