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CPU-FPGA heterogeneous architectures are attracting ever-increasing attentionin an attempt to advance computational capabilities and energy efficiency intoday's datacenters. These architectures provide programmers with the abilityto reprogram the FPGAs for flexible acceleration of many workloads.Nonetheless, this advantage is often overshadowed by the poor programmabilityof FPGAs whose programming is conventionally a RTL design practice. Althoughrecent advances in high-level synthesis (HLS) significantly improve the FPGAprogrammability, it still leaves programmers facing the challenge ofidentifying the optimal design configuration in a tremendous design space.  This paper aims to address this challenge and pave the path from softwareprograms towards high-quality FPGA accelerators. Specifically, we first proposethe composable, parallel and pipeline (CPP) microarchitecture as a template ofaccelerator designs. Such a well-defined template is able to support efficientaccelerator designs for a broad class of computation kernels, and moreimportantly, drastically reduce the design space. Also, we introduce ananalytical model to capture the performance and resource trade-offs amongdifferent design configurations of the CPP microarchitecture, which lays thefoundation for fast design space exploration. On top of the CPPmicroarchitecture and its analytical model, we develop the AutoAccel frameworkto make the entire accelerator generation automated. AutoAccel accepts asoftware program as an input and performs a series of code transformationsbased on the result of the analytical-model-based design space exploration toconstruct the desired CPP microarchitecture. Our experiments show that theAutoAccel-generated accelerators outperform their corresponding softwareimplementations by an average of 72x for a broad class of computation kernels.

AutoAccel: Automated Accelerator Generation and Optimization with Composable, Parallel and Pipeline Architecture