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Packet parsing is a key step in SDN-aware devices. Packet parsers in SDNnetworks need to be both reconfigurable and fast, to support the evolvingnetwork protocols and the increasing multi-gigabit data rates. The combinationof packet processing languages with FPGAs seems to be the perfect match forthese requirements. In this work, we develop an open-source FPGA-basedconfigurable architecture for arbitrary packet parsing to be used in SDNnetworks. We generate low latency and high-speed streaming packet parsersdirectly from a packet processing program. Our architecture is pipelined andentirely modeled using templated C++ classes. The pipeline layout is derivedfrom a parser graph that corresponds a P4 code after a series of graphtransformation rounds. The RTL code is generated from the C++ description usingXilinx Vivado HLS and synthesized with Xilinx Vivado. Our architecture achieves100 Gb/s data rate in a Xilinx Virtex-7 FPGA while reducing the latency by 45%and the LUT usage by 40% compared to the state-of-the-art.

P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs