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Bayesian Neural Networks (BNNs) have been proposed to address the problem ofmodel uncertainty in training and inference. By introducing weights associatedwith conditioned probability distributions, BNNs are capable of resolving theoverfitting issue commonly seen in conventional neural networks and allow forsmall-data training, through the variational inference process. Frequent usageof Gaussian random variables in this process requires a properly optimizedGaussian Random Number Generator (GRNG). The high hardware cost of conventionalGRNG makes the hardware implementation of BNNs challenging.  In this paper, we propose VIBNN, an FPGA-based hardware accelerator designfor variational inference on BNNs. We explore the design space for massiveamount of Gaussian variable sampling tasks in BNNs. Specifically, we introducetwo high performance Gaussian (pseudo) random number generators: the RAM-basedLinear Feedback Gaussian Random Number Generator (RLF-GRNG), which is inspiredby the properties of binomial distribution and linear feedback logics; and theBayesian Neural Network-oriented Wallace Gaussian Random Number Generator. Toachieve high scalability and efficient memory access, we propose a deeppipelined accelerator architecture with fast execution and good hardwareutilization. Experimental results demonstrate that the proposed VIBNNimplementations on an FPGA can achieve throughput of 321,543.4 Images/s andenergy efficiency upto 52,694.8 Images/J while maintaining similar accuracy asits software counterpart.

VIBNN: Hardware Acceleration of Bayesian Neural Networks