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Hardware accelerators are key to the efficiency and performance ofsystem-on-chip (SoC) architectures. With high-level synthesis (HLS), designerscan easily obtain several performance-cost trade-off implementations for eachcomponent of a complex hardware accelerator. However, navigating this designspace in search of the Pareto-optimal implementations at the system level is ahard optimization task. We present COSMOS, an automatic methodology for thedesign-space exploration (DSE) of complex accelerators, that coordinates bothHLS and memory optimization tools in a compositional way. First, thanks to theco-design of datapath and memory, COSMOS produces a large set of Pareto-optimalimplementations for each component of the accelerator. Then, COSMOS leveragescompositional design techniques to quickly converge to the desired trade-offpoint between cost and performance at the system level. When applied to thesystem-level design (SLD) of an accelerator for wide-area motion imagery(WAMI), COSMOS explores the design space as completely as an exhaustive search,but it reduces the number of invocations to the HLS tool by up to 14.6x.

COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators