English (United Kingdom)

https://curated-unify.zendy.io/wp-json/zendy-region/v1/featured_content/oa?rat=en

https://curated-unify.zendy.io/wp-json/zendy-region/v1/highlighted_journal/

Zendy Plus

Presents the zaia usage as premium feature

ZAIA

Presents the pdf analysis as premium feature

PDF Analysis

Insights

Presents the summarisation as premium feature

Summarisation

Presents the keyphrase highlighting as premium feature

Keyphrase Highlighting

Presents the access of premium content as premium feature

Premium Content

Zendy Tools

Zendy Open

The idea of coupling reconfigurable fabrics with general-purpose processors has been extensively studied during the last couple of decades. Custom instructions targeting those reconfigurable fabrics had to be handcrafted because tools capable of high level synthesis were not available at the time. Nowadays, high level synthesis tools have matured to a state allowing system designers to automatically generate hardware implementations from software applications. At the end of Moore's era, it is required to reinvestigate reconfigurable custom instructions by taking full advantage of the latest HLS compilers. In this paper we introduce the concept of CPU interlays which are FPGA-like fabrics that are integrated directly into the core of a hardened processor. This enables the customization of an instruction set at run-time. While CPU interlays will show best performance with hand-optimized custom instructions, this paper suggests a semi-automated flow that does not need the expertise of an FPGA designer. Using automatic profiling together with HLS tools allows the acceleration of user programs with very little human interaction during application design. By replacing the NEON SIMD unit of an ARM Cortex-A9 with an interlay taking the same die area, we could demonstrate speedups as high as 68x for individual function kernels without touching any RTL code. Furthermore, we show that while HLS compilers can enhance design productivity, it is in some cases required to follow a HLS-friendly coding style for maximizing performance.

HLS Compilation for CPU Interlays