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This paper presents a novel approach for synthesis of analogsys- tems from behavioral VHDL-AMS specifications. We implement ed this approach in the VASE behavioral-synthesis tool. The sy nthe- sis process produces a netlist of electronic components tha t are selected from a component library and sized such that the ove rall area is minimized and the rest of the performance constraint s such as power, slew-rate, bandwidth, etc. are met. The gap betwee n system level specifications and implementations is bridged using a hierarchically-organized, design-space exploration met hodology. Our methodology performs a two-layered synthesis, the first being architecture generation, and the other component synthesi s and constraint transformation. For architecture generation w e sug- gest a branch-and-bound algorithm, while component synthe sis and constraint transformation use a Genetic Algorithm based he uristic method. Crucial to the success of our exploration methodolo gy is a fast and accurate performance estimation engine that em beds technology process parameters, SPICE models for basic circ uits and performance composition equations. We present a teleco m- munication application as an example to illustrate our synt hesis methodology, and show that constraint-satisfying designscan be synthesized in a short time and with a reduced designer effor t. The complex task of synthesizing analog and mixed analog-digital systems is typically approached using a hierarchically org anized top-down design paradigm, across successive levels of abstraction (5) (11). In the most general case, such a synthesis environment starts from specifications and design/performance constraints at the system-level, moves down to the circuit-level, and finally considers the layout-level. Recent research on analog synthesis exclusively targets circuit-synthesis and layout generation, which ar e design activities at lower levels of abstraction. Circuit synthes is (14) (19) (20) assumes a known circuit-topology, and searches for physi- cal dimensions of transistors, so that circuit-level perfo rmance at- tributes, i.e. bandwidth, slew-rate, power, are optimized . Layout tools (6) perform cell placement and routing, with respect t o phys- ical constraints, i.e. parasitics, cross-talk, latch-up. However, for achieving automated analog-system synthesis or mixed-signal syn- thesis, bridging the gap between system and circuit level designs becomes of crucial importance. Traditionally, this task is known as High Level Synthesis(HLS). This work is sponsored by USAF, Air Force Research Laboratory, WPAFB under

Behavioral synthesis of analog systems using two-layered design space exploration