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This paper explores a standard-cell design methodology based on netlist partitioning as a solution for the problem of lack of convergence in the conventional methodology in deep submicron technologies. A synthesized design block is partitioned along unpredictable nets that are identified from the netlist structure. The size of each partition is restricted so that the longest possible local net in a partition can be sufficiently driven by an average library gate, hence allowing statistical wire-load modeling for the local nets. The block is resynthesized using a hybrid wire-load model that takes into a~count accurate wire-load information on the unpredictable nets derived after floorplanning the partitions, and uses custom statistical wire-load models within each partition. Final placement is restricted to respect the initial floorplan. The methodology was implemented using existing commercial tools for synthesis and layout. Experimental results show high correlation between synthesis estimates and post-placement measurements of wire-loads and gate delays with the new methodology. The trade-offs of partitioning, current limitations of the methodology and future work to overcome these limitations are also discussed.

Using partitioning to help convergence in the standard-cell design automation methodology