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In this paper, we consider the problem of generating small (compact) test sets for single transition and CMOS stuck-open faults in combinational logic circuits. In addition, we propose that to generate test sets that cover a wide range of physical defects, a test set to detect faults of different models should be derived. Specifically, we address the problem of generating small and comprehensive test sets by considering the CMOS stuck-open and the single transition fault models together. We propose a dynamic test compaction technique for two-pattern tests, which exploits the test compaction strategies developed for stuck-at faults, and performs dynamic test vector overlap to derive small test sets. We present experimental results for ISCAS-85 combinational circuits and fully scanned versions of ISCAS-89 sequential circuits to illustrate the efficacy of the proposed test compaction technique.

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits