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Linear state variable digital systems, commonly implemented in bit-serial architecture using silicon compilers, are difficult to test for manufacturing defects due to deep sequentiality, low controllability and observability, and high latency. A novel hierarchical testing approach, based on matrix manipulation and constrained low-level test generation, is reported here. FEAST (Functional Extractor and Sequential Test generator) operates at the high level, where the circuit is described as an interconnection of arithmetic modules. CREST (Constrained Sequential Test generator) operates at the low level description of the individual modules, and generates test sets satisfying constraints imposed by the high-level modules and their interconnection structure. The new approach was found to perform better when compared to automatic test generation at the gate level using existing algorithms for several large circuits.

Automatic test generation for linear digital systems with bi-level search using matrix transform methods