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Full scan design technique alleviates the test generation problem for sequential circuits. However scan operations increase the number of test clocks substantially. This paper presents an algorithm to generate a test with fewer test clocks for full scan designs by using combinational and sequential test generation algorithms adaptively. Heuristics combining test measures and scan strategies are introduced. The algorithm, Test Application time Reduction for Full scan designs (TARF), is implemented and tested on a set of ISCAS sequential benchmark circuits. The results show that TARF achieves same test coverage as combinational test generators but with fewer test clocks.

An algorithm to reduce test application time in full scan designs