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FPGA users often view the ability of an FPGA to route designs with high LUT (gate) utilization as a feature, leading them to demand high gate utilization from vendors. We present initial evidence from a hierarchical array design showing that high LUT utilization is not directly correlated with efficientsilicon usage. Rather, since interconnect resources consume most of the area on these devices (often 80-90%), we can achieve more area efficientdesigns by al- lowing some LUTs to go unused—allo wing us to use the dominant resource, interconnect, more efficiently. This extends the "Sea-of- gates" philosophy, familiar to mask programmable gate arrays, to FPGAs. Also introduced in this work is an algorithm for "depop- ulating" the gates in a hierarchical network to match the limited wiring resources.

Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)