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Stencil algorithms on regular lattices appear in many fields of computationalscience, and much effort has been put into optimized implementations. Suchactivities are usually not guided by performance models that provide estimatesof expected speedup. Understanding the performance properties and bottlenecksby performance modeling enables a clear view on promising optimizationopportunities. In this work we refine the recently developedExecution-Cache-Memory (ECM) model and use it to quantify the performancebottlenecks of stencil algorithms on a contemporary Intel processor. Thisincludes applying the model to arrive at single-core performance andscalability predictions for typical corner case stencil loop kernels. Guided bythe ECM model we accurately quantify the significance of "layer conditions,"which are required to estimate the data traffic through the memory hierarchy,and study the impact of typical optimization approaches such as spatialblocking, strength reduction, and temporal blocking for their expectedbenefits. We also compare the ECM model to the widely known Roofline model.

Quantifying performance bottlenecks of stencil computations using the Execution-Cache-Memory model