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In timing-driven layout synthesis, transistor sizes tend to besignificantly different from each other and thus the use of conventionallayout approaches can cause inefficient area utilization.We propose an efficient algorithm to find the optimaltransistor folding sizes in row-based designs.Our algorithmfinds optimal folding sizes given a CMOS circuit with m pairsof pMOS and nMOS transistors in O(m{2} log m) time complexitywith the effective reduction of the solution space.MCNCbenchmark circuits are used to demonstrate the area-efficiencyof the physical layouts with optimal folding sizes.

An efficient transistor folding algorithm for row-based CMOS layout design