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This paper presents new results in constraint-directed placement and routing of device-level analog cells. We describe the jirst algorithm for latchup-aware device placement that guarantees suficient placement of welltsubstrate contacts by simultaneous placement of latchup protection geometry and devices. A novel cost-to-target predictor for cost-breed A* routing, and a new scheme for pruning evolving paths that violate user-supplied parasitic bounds, combine to allow faster, deeper, more tightlyconstrained routing of arudog signals in ahse placements. Experimental results suggest the strategy avoids the art~acts of length-for-crosstalk tra&-offs seen in earlier algorithms, and allows users more fine-grain control of the routing of dense, highperformance cells. An implementation of these ideas in thetool set KAIII is used to derive improved layouts from several analog

Latchup-aware placement and parasitic-bounded routing of custom analog cells