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This paper studies techniques to improue the performance of memory consistency models for shared-memory multi- processors with ILP processors. The first part of this pa- per extends earlier work by studying the impact of current hardware optimization to memory consistency implementa- tions, hardware-controlled non-binding prefetching and spec- ulative load execution, on the performance of the processor consistency (PC) memory model. We find that the opti- mized implementation of PC performs significant tly better than the best implementation of sequential consistency (SC) in some cases because PC relaxes the store-to-load ordering constraint of SC. Nevertheless, release consistency (RC) pro- vides significant benefits over PC in some cases, because PC' suffers from the negative ef7ects of premature store prefetches and insufficient memory queue sizes. The second part of the paper proposes and evaluates a new technique, speculative retirement, to improve the per- formance of SC. Speculative retirement alleviates the im- pact of the store-to-load constraint of SC by allowing loads and subsequent instructions to speculatively commit or re- tire, even while a previous store is outstanding. Speculative retirement needs additional hardware support (in the form of a history bu~er) to recover from possible consistency viola- tions due to such speculative retires. With a 64 element his- tory bufler, speculative retirement reduces the execution time gap between SC and PC to within 11% for ail our applica- tions on our base architecture; a significant, though reduced, gap still remains between SC and RC. The third part of our paper evaluates the interactions of the various techniques with larger instruction window sizes. When increasing instruction window size, initially, the pre- vious best implementations of all models generally improve in performance due to increased load and store overlap. With further increases, the performance of PC and RC stabilizes while that of SC often degrades (due to negative eflects of

Using speculative retirement and larger instruction windows to narrow the performance gap between memory consistency models