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Power dissipation is an important parameter in the design of VLSI circuits, and the clock network is responsible for a substantial part of it (upto 50%). Two main approaches have been suggested to reduce clock dissipation: clock gating and low power flip-flops. In this article we address the latter. We demonstrate that the usage of double edge triggered flip-flops results in a power reduction of 50% in the clock net, and in a reduction of upto 45% inside the flip-flops. Furthermore, we consider other flip-flop parameters, like setup and hold times, propagation delay and testability. 1 Introduction and Motivation With the growing integration of today's VLSI circuits, power dissipation is gaining importance. Power dissipation is becoming one of the limiting factors for further integration, since high dissipation values lead to high temperatures and reduce the lifetime of integrated circuits (ICs). Furthermore, battery-powered applications require low-energy consuming ICs. The power dissipation in synchronous VLSI circuits is contributed by several factors: i.e. memory, IO, logic and clock power dissipation. The memory power dissipation can be reduced by designing less power consuming memories, and/or by reducing the number of memory accesses of the implemented algorithm (Cha95). A similar approach must be followed for the IO power dissipation. There are many ways to reduce the logic power dissipation (Dev95), and this is the field towards most research on low power design is targeted. Clock dissipation is divided into three major contributions: that of clock wires, clock buffers and flip-flops. Each of these contributions is described in the following paragraph.

Low power, testable dual edge triggered flip-flops