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A low-power Frequency Multiplier (FMUL) with 100 ppm frequency resolution, +/-100 ps jitter, and one cycle frequency lock-in time is presented. It is used to generate clock frequencies up to 100 MHz using a reference frequency of 32,768 Hz, for advanced power management both at a device level and at a system level. The FMUL is implemented in a standard digital CMOS process and its area is 0.5 mm2 @ 0.8 . Introduction Power management and low-power design have become a critical requirement, and a key differentiator, in a range of application. These include: portable Personal Computers (PCs), desktop “green” PCs, and other portable, battery operated, devices. The objective of power management in portable, battery operated, systems is to extend the battery life to the maximum, while retaining the required functionality. Moreover, since most portable PCs today use passive cooling techniques, power management and lowpower design are essential for system thermal management. Furthermore, PCs are on a route to converging into a multi-functional home appliance, providing computing services, networking and communication services, entertainment services, and eventually, control and monitoring of other home appliances, such as, security systems, etc. This would require that the system would never be turned off. To enable such applications, advanced power management techniques, coupled with very low-power design would be a most critical requirement. The conventional power management techniques include: removing the power supply from idle devices, and stopping the clock to idle devices or modules, based on activity monitoring timers. This is sometimes referred to as passive power management. The more advanced and complex approach, is the active power management, by which power consumed by the system, or device, is reduced while it is actively in use. Active power management enables system OEMs and semiconductor suppliers to further reduce power consumption, beyond the level which is achieved using passive power management techniques, and use it as a major competitive advantage and a key differentiator. Active power management requires a run-time, programmable, control of the clock frequency. This means that the clock frequency is reduced, or increased, according to the required performance and functionality of the system or the device. Moreover, the transitions in the clock frequency need to be done instantly and in a manner which is totally transparent to the user. The FMUL presented here, meets all of the above requirements while consuming very low power itself. It uses a reference clock of 32,768 Hz to generate clock frequencies up to 100 MHz. In one typical application, the presented FMUL is employed in the implementation of a power management and system controller, which uses three main modes of operation: (i) Fully-on mode: In which the operating frequency ranges between 5-10 MHz (ii) Idle mode: In which the operating frequency is reduced to 1 MHz (iii) Power-Save mode: In which the operating frequency is 32,768 Hz. The controller’s transitions from one operation mode to the other is triggered by hardware events, but managed by the firmware which also changes the clock frequency by programming the FMUL registers according to the desired operating frequency. Some additional values of the presented circuit include: reducing system cost by eliminating high frequency crystals, which also reduces the Electro-Magnetic-Interference (EMI). Typically, on-chip high frequency generators, using low frequency external reference clock, are implemented by a PLL [1]-[5]. However, in those applications where there is no need to correlate the phase between the high and low frequency clocks, like for instance embedded system controllers and PC I/O peripherals, it will be preferable to use the FMUL approach, rather than the PLL approach. The FMUL presented here is based on [6]. It generates a high frequency clock by means of digitally controlled current-controlled-oscillator (CCO). This frequency is controlled directly and not by its phase leg/lead, as done in a PLL. μm Low-Power Frequency Multiplier with One Cycle Lock-In Time and 100 ppm Frequency Resolution, for System Power-Management Rafael Fried1 and Ziv Azmanov 2 1 EPFL Swiss Federal Institute of Technology, Department of Electrical Engineering, DE-LEG, 1015 Lausanne, Switzerland 2 National Semiconductor, 1090 Kifer Road, Sannyvale, CA-94086, USA ISLPED 1996 Monterey CA USA 0-7803-3571-8/96/$5.00  1996 Its main advantage over the conventional PLLs is the fact that theoretically unlimited frequency multiplication factors can be achieved while keeping very high frequency resolution, in the order of 100 ppm, and low current consumption. Trying to use PLL for the same task will cause instability problems, and consume very large area. Additional advantages of the FMUL presented here, compared to a PLL, are the much shorter lock-in time, perfectly smooth clock transitions, and no need for additional external components for the loop filter, as needed when using a PLL to achieve high multiplication factors (low frequency reference clocks). Furthermore, the FMUL’s performance is almost not affected by process parameters and supply voltage variations, and its stability is guarantied. In this paper the basic principle of the FMUL is reviewed. Its accuracy and jitter causes are analyzed. Limitations to power consumption reduction are given. Solutions to achieve one cycle frequency lock-in time, and a solution to prevent discontinuity problems in the frequency curve, are presented. Results are shown. Digitally Controlled Frequency Multiplier The FMUL’s complete block diagram is presented in Fig.1. It consists of three modules: (i) the CCO,(ii) the CCO digital control logic, and(iii) the arithmetic module that is responsible for the one cycle frequency lock-in time. Frequency locking is done in two phases, the first is coarse tuning, and the second is fine tuning. During the coarse tuning a binary search algorithm is implemented in a similar way to a successive approximation DAC, and during the fine tuning the frequency is incremented/decremented by small constant steps. The coarse tuning is done only once, during the chip’s reset cycle. The CCO configuration is a shmidt-trigger based current-driven oscillator, as shown in Fig. 2 [6]. The high frequency resolution is achieved by using 14 binary weighted current sources at the CCO, that operates similarly to a 14bit DAC. However, in the FMUL presented here, as opposed to a DAC, neither linearity nor monotony of the high order bits is necessary. The capacitor’s charging current Icrg, is digitally controlled by the value of the 14 bit control word S (S0-S13 in Fig. 2). The discharge current Idis, is constant, as given by (1), whereI0 is the value of the charge current LSB, A is a constant and A>>max{S}.

Low-power frequency multiplier with one cycle lock-in time and 100ppm frequency resolution, for system power-management