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In this paper the e ects of technology scaling on the fraction of active power Pa wasted as short-circuit power Ps are studied through SPICE simulations. The accuracy of SPICE is veri ed against experimental data. SPICE simulations show that lowering VT below 0.1V can increase Ps=Pa signi cantly beyond what is expected from increased subthreshold leakage. Ps=Pa is typically higher at higher Vcc but to rst order Ps=Pa is determined by signal slew rates and VT . It is shown that the input slew rate is constrained by Ps=Pa at low VT and by performance at higher VT . We show that Ps increases with increasing gate sheet resistance. A simple analytical model for this e ect is veri ed against the experimental data and used to determine the gate sheet requirements to maintain Ps/Pa < 10% for sub-0.25 m technologies.

An investigation of the impact of technology scaling on power wasted as short-circuit current in low voltage static CMOS circuits