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We present a low-power SRAM design based on the theory of energy recovery that reduces the dissipation associated with write operations while operating at high speed. The energy-recovery SRAM was evaluated through SPICE simulations and compared with a standard design. Simulation results of a 256 ×256 memory configuration indicate that, for successive write operations, energy savings for the different SRAM functions vary from 59% to 76% at 200 MHz operating frequency compared to the conventional design.

Energy recovery for the design of high-speed, low-power static RAMs