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Digital's Alpha-based DECchip 21164 processor was verified extensively prior to fabrication of silicon. This simulation-based verification effort used implementation-directed, pseudorandom exercisers which were supplemented with implementation- specific, hand-generated tests. Special emphasis was placed on the tasks of checking for correct operation and functional coverage analysis. Coverage analysis shows where testing is incomplete, under the assumption that untested logic often contains bugs. Correctness checkers are various mechanisms (both during and after simulation) that monitor a test to determine if it was successful. This paper details the coverage analysis and correctness checking techniques that were used. We show how our methodology and its implementation was successful, and we discuss the reasons why this methodology allowed several minor bugs to escape detection until the first prototype systems were available. These bugs were corrected before any chips were shipped to customers. OVERVIEW The DECchip 21164 CPU chip is a quad-issue, super-scalar implementation of the Alpha architecture which required a rigorous verification effort to ensure that there were no logical bugs. World-class performance dictated the use of many advanced micro-architectural features, such as a virtual instruction cache with seven-bit Address Space Numbers, a dual-read-ported data cache, out-of-order instruction completion, on-chip three-way set-associative write-back second-level cache, module-level cache control, branch prediction, demand-paged memory management unit, write buffer unit, miss-address file unit, and a complicated Bus Interface Unit with support for various CPU-system clock ratios, system configurations, and module-level cache parameters. (1) Increasingly, functional verification efforts are relying on pseudorandom test generation to improve the quality of functional coverage. These techniques have been in use at Digital for more than seven years and are also used elsewhere in the industry and in academia.(2-5) However, the heavy use of pseudorandom testing increases the need for new ways of determining whether the test passed or failed, and new ways of determining exactly what portion of the design the test actually exercised. This paper discusses the correctness checking and coverage analysis mechanisms used by the DECchip 21164 verification team to ensure adequate functional coverage using pseudorandom test generators. VERIFICATION PROCESS

I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor