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We consider the problem of transistor sizing in a static CMOS layout to minimize the power consumption of the circuit subject to a given delay constraint. Based on our characterization of the short circuit power dissipation of a CMOS circuit we show that the transistors of a gate with high fan-out load should be enlarged to minimize the power consumption of the circuit. We derive analytical formulation for computing the power optimal size of a transistor and isolate the factor a ecting the power optimal size. We extend our model to analyze powerdelay characteristic of a CMOS circuit and derive the power-delay optimal size of a transistor. Based on our model we develop heuristics to perform transistor sizing in CMOS layouts for minimizing power consumption while meeting given delay constraints. Experimental results (SPICE simulations) are presented to con rm the correctness of our analytical model.

Transistor sizing for minimizing power consumption of CMOS circuits under delay constraint