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This paper shows that cascade circuits in the logic cells of all current lookup table based FPGAs support only linear cascading chain and, as a result, contribute to long cascading delay. We present an enhanced cascade circuit that will reduce cascading delay significantly: from linear time to log time in terms of the number of logic cells cascaded. We show that the additional area for the new cascade circuit is very small. We discuss an interaction between architecture design decision and CAD (in particular, placement) for the design of dedicated routing structure for cascade signals between logic cells. We illustrate the advantage of the new cascade circuit with an example of 32-bit equality checking circuit.

Revisiting the cascade circuit in logic cells of lookup table based FPGAs