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In this paper, we propose a novel algorithm for synthesizing the pipeline structures with variable data initiation intervals (DIIs). Compared to previous researches where the pipeline synthesis is confined to those with fixed DIIs, the proposed algorithm tries to optimize the pipeline latency by fully utilizing hardware resources to which abstract operations in high-level design descriptions are assigned. Determining time-overlapping of pipeline stages, the proposed algorithm performs scheduling and module allocation using the time-overlapping information for the proper control of pipelines with variable DIIs. Experimental results on benchmarks show that significant improvement can be achieved both in speed and in area.

Automatic synthesis of pipeline structures with variable data initiation intervals