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This paper describes CLARION, a circuit reorganization subsystem of the USe-Test system. Most digital circuit designs are described as netlists of hundreds of thousands of gates and flip-flops, and CAD tools and engineers often do not have knowl- edge of the high-level structure of the design. Starting from only a flat description of a circuit, CLARION constructs a 2-level hierarchy of the dataflow struc- ture of the circuit consisting of registers and blocks of connected combinational logic. This circuit reor- ganization capability has applications in CAD areas such as floorplanning, placement, routing, retiming and logic resynthesis. An application to the high- level design-for-testa bility (DFT) and built-in self-test (BIST) tools in the USC-Test system is presented.

Extraction of a high-level structural representation from circuit descriptions with applications to DFT/BIST