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The problem of delay fault-testing and detection of chips with marginal performance has become even more critical than before due to advancing clock speeds. In this paper, a methodology for detection of marginal digital circuits and diagnosis of gate delay failures is developed. A new test application methodology is proposed in which test vectors may be applied to digital combinational circuits at intervals smaller than the critical path delay of the circuit and signal waveform analysis is used to interpret the test results. The resulting tests are called RApid Fire Tests (for RAFT) and allow classification of circuits from “good” to “bad” along a continuous scale.

RAFT191486: a novel program for rapid-fire test and diagnosis of digital logic for marginal delays and delay faults