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In analog system design, final verification in the presence ofpara- sitic loading effects is crucial to guarantee functionalit y of the entire circuit. In this paper, we present a methodology for analog s ystem verification in the presence of parasitics using behavioral simulation. When applied to a synthesized 10 bit D/A, our approach is accurate to 0.005 LSB compared with SPICE, while being several orders of magnitude faster. component can often be verified with SPICE. After we verify each component against its specifications, we check the system performance in the presence of layout parasitics. This last step has been carried out in the past at the SPICE simulation level. In this paper, we propose a new methodology that uses behavioral models of the components and behavioral simulation. The benefits of the approach are overwhelming when compared to SPICE level simulation. Section 2 introduces the new verification strategy, followed by the application of the strategy to verification of Nyquist D/A converters in Section 3. Experimental results are presented in Section 4, followed by a conclusion in Section 5. 2 Verification in the presence of parasitics between components

Analog system verification in the presence of parasitics using behavioral simulation