Dual-threshold pass-transistor logic design

This paper introduces pass-transistor logic design with dual-threshold voltages. A set of single-rail, fully restored, pass-transistor gates are presented. Logic transistors are implemented with low threshold voltages and signal restoration transistors with high threshold voltages. Simulation is used to characterize the leakage power consumption, switching energy, and propagation delay of the proposed gates. A method to reduce circuit power by selectively replacing CMOS gates with the proposed gates is discussed and applied to the ISCAS'85 benchmark circuits. Relative to circuits composed entirely of conventional CMOS gates, use of the proposed SDPL gates achieves up to 49% reduction in leakage power and up to 63% reduction in total power consumption.