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Power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. This work aims to analyze and establish the relations between the three important design parameters in power gated circuits: (i) the maximum current flowing from/to power/ground (ii) the wakeup (sleep to active mode transition) time delay and (iii) the number of sleep transistors. With the understanding of relations between the parameters, we propose solutions to the two problems: (1) finding logic clusters and their wakeup schedule to minimize the sleep transistor overhead under the constraints of wakeup time and peak current and (2) finding logic clusters and their wakeup schedule to minimize the wakeup time under the constraints of peak current and the number of sleep transistors. From an experimentation using ISCAS benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 65% ~ 77% reduced number of sleep transistors and 30% ~ 36% reduced wakeup time delay, compared to the results by the previous work.

Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits