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The access time for content addressed data can be significantly improved if it is filed according to an appropriate set of descriptors. A further improvement can be obtained if hardware, rather than software, techniques are used to implement the file or sorting memory. The paper discusses the design of a hardware implemented system which can sort and re-sort digital data according to any set of descriptors chosen. The main limitation to the speed of sorting and re-sorting is the intercommunication system between the various parts of the store. The application of segmented ring bus techniques gives a high sorting speed and a flexible system. The memory design is suitable for LSI because it consists of a number of similar units capable of integration using silicon technology.

A data sorting system using a high speed bus