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Power gating is an efficient technique for reducing leakage power in electronic devices by disconnecting blocks idle for long periods of time from the power supply. Disconnecting gated blocks causes changes in densities of currents flowing through a grid. Even in DC conditions, current densities in some grid branches may increase for some gating configurations to the extent of violating electromigration (EM) constraints. The existing DC methods for grid sizing optimize the grid area under voltage drop (IR) and EM constraints for one configuration of circuit blocks connected to the grid. We show that these methods cannot be directly applied for optimizing power-gated grids. We analyze the effects of EM and IR voltage drop in power grids with multiple power gating configurations. Based on our analyses, we develop a grid sizing algorithm to satisfy all reliability constraints for all feasible gating configurations. Our experimental results indicate that a grid initially sized for all blocks present may be modified to fulfill EM and IR constraints for multiple gating schedules with only a small area increase.

Analysis and optimization of power-gated ICs with multiple power gating configurations